Julian Oppermann

Brindusa Mihaela Damian-Kosterhon

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

Altis-SYCL: Migrating Altis Benchmarking Suite from CUDA to SYCL for GPUs and FPGAs.

[BibT_eX]

[DOI]

Christoph Weckert

Leonardo Solis-Vasquez

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

2022

The Scale4Edge RISC-V Ecosystem.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

2019

Active Storage.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Big Data Technologies., 2019

Advances in ILP-based Modulo Scheduling for High-Level Synthesis.

[BibT_eX]

[DOI]

PhD thesis, 2019

Exact and Practical Modulo Scheduling for High-Level Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2019

SpExSim: assessing kernel suitability for C-based high-level hardware synthesis.

[BibT_eX]

[DOI]

J. Supercomput., 2019

Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis.

[BibT_eX]

[DOI]

Lukas Weber

Proceedings of the International Conference on Field-Programmable Technology, 2019

Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling.

[BibT_eX]

[DOI]

Patrick Sittel

Martin Kumm

Proceedings of the Euro-Par 2019: Parallel Processing, 2019

Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

2018

Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

ILP-Based Modulo Scheduling and Binding for Register Minimization.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Dependence Graph Preprocessing for Faster Exact Modulo Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Extending Database Technology, 2018

GeMS: a generator for modulo scheduling problems: work in progress.

[BibT_eX]

[DOI]

Sebastian Vollbrecht

Proceedings of the International Conference on Compilers, 2018

Improved High-Level Synthesis for Complex CellML Models.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017

Synthesis of interleaved multithreaded accelerators from OpenMP loops.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016

Performance optimisation strategies for automatically generated FPGA accelerators for biomedical models.

[BibT_eX]

[DOI]

Concurr. Comput. Pract. Exp., 2016

Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, 2016

ILP-based modulo scheduling for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

2015

Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Automatic high-level synthesis of multi-threaded hardware accelerators.

[BibT_eX]

[DOI]

Jens Huthmann