Julian J. H. Pontes

According to our database, Julian J. H. Pontes authored at least 15 papers between 2007 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

IEEE J. Solid State Circuits, 2021

2020

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm² Inter-Chiplet Interconnects and 156mW/mm²@ 82%-Peak-Efficiency DC-DC Converters.

Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2015

Two-phase protocol converters for 3D asynchronous 1-of-n data links.

Julian J. H. Pontes, Pascal Vivet, Yvain Thonnart

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design.

Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013

H2A: A hardened asynchronous network on chip.

Julian J. H. Pontes, Ney Calazans, Pascal Vivet

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Parity check for m-of-n delay insensitive codes.

Julian J. H. Pontes, Ney Calazans, Pascal Vivet

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

2012

Soft error mitigation in asynchronous networks on chip.

Julian J. H. Pontes

PhD thesis, 2012

An accurate Single Event Effect digital design flow for reliable system level design.

Julian J. H. Pontes, Ney Calazans, Pascal Vivet

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects.

Julian J. H. Pontes, Ney Calazans, Pascal Vivet

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011

A 65nm standard cell set and flow dedicated to automated asynchronous circuits design.

Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Ney Calazans

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Adapting a C-element design flow for low power.

Matheus T. Moreira, Bruno Cruz de Oliveira, Julian J. H. Pontes, Fernando Moraes, Ney Calazans

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.

Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Hermes-A - An Asynchronous NoC Router with Distributed Routing.

Julian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2008

Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques.

Julian J. H. Pontes, Matheus T. Moreira, Rafael Soares, Ney Laert Vilar Calazans

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.

Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans

Proceedings of the 25th International Conference on Computer Design, 2007