Julia Dushina
According to our database1,
Julia Dushina
authored at least 6 papers
between 1998 and 2003.
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Bibliography
2003
Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial application.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 38th Design Automation Conference, 2001
2000
A compositional model for the functional verification of high-level synthesis results.
IEEE Trans. Very Large Scale Integr. Syst., 2000
1999
Vérification formelle des résultats de la synthèse de haut niveau. (Formal verification of high level synthesis results).
PhD thesis, 1999
1998
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998