Jukka Teittinen
According to our database1,
Jukka Teittinen
authored at least 5 papers
between 2014 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
2014
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2020
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020
2017
Microelectron. J., 2017
2016
A Performance Case-Study on Memristive Computing-in-Memory Versus Von Neumann Architecture.
Proceedings of the 2016 Data Compression Conference, 2016
2014
SIGMOD Rec., 2014
A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014