Juhyun Park
Orcid: 0000-0001-7112-6493
According to our database1,
Juhyun Park
authored at least 26 papers
between 2007 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
2022
SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Analysis of variability in sign language hand trajectories: development of generative model.
Proceedings of the MOCO '22: 8th International Conference on Movement and Computing, Chicago, IL, USA, June 22, 2022
2021
A regularized functional regression model enabling transcriptome-wide dosage-dependent association study of cancer drug response.
PLoS Comput. Biol., 2021
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation.
IEEE Access, 2021
2020
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
IEEE Access, 2020
2019
IEEE J. Solid State Circuits, 2019
Proceedings of the Geometric Science of Information - 4th International Conference, 2019
2018
New flash memory acquisition methods based on firmware update protocols for LG Android smartphones.
Digit. Investig., 2018
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015
SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2009
2007
Comput. Stat. Data Anal., 2007