Juhyoung Lee
Orcid: 0000-0002-2100-1024
According to our database1,
Juhyoung Lee
authored at least 39 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell.
IEEE J. Solid State Circuits, January, 2024
2023
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit.
IEEE J. Solid State Circuits, October, 2023
NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
TSUNAMI: Triple Sparsity-Aware Ultra Energy-Efficient Neural Network Training Accelerator With Multi-Modal Iterative Pruning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Low-Power Graph Convolutional Network Processor With Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor.
IEEE Micro, 2022
A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation.
IEEE Micro, 2022
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer.
IEEE J. Solid State Circuits, 2022
HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile Devices.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
A DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks.
IEEE J. Solid State Circuits, 2021
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation.
IEEE J. Solid State Circuits, 2021
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching.
IEEE J. Solid State Circuits, 2021
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021
An Energy-Efficient Deep Reinforcement Learning FPGA Accelerator for Online Fast Adaptation with Selective Mixed-precision Re-training.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
Energy-Efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
SRNPU: An Energy-Efficient CNN-Based Super-Resolution Processor With Tile-Based Selective Super-Resolution in Mobile Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping Based Dilated Graph Convolutional Network for Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture.
IEEE Micro, 2018
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017
2004
Proceedings of the 2004 IEEE International Conference on Robotics and Automation, 2004