Juha Plosila

Proceedings of the Genetic and Evolutionary Computation Conference, 2012

NoC-AXI interface for FPGA-based MPSoC platforms.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

HLS-DoNoC: High-level simulator for dynamically organizational NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

ARB-NET: A novel adaptive monitoring platform for stacked mesh 3D NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Analysis of Monitoring Structures for Network-on-Chip: A Distributed Approach.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2011

Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2011

Agent-based on-chip network using efficient selection method.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Exploration of MPSoC monitoring and management systems.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Efficient congestion-aware selection method for on-chip networks.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

High-performance on-chip network platform for memory-on-processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Analysis of Status Data Update in Dynamically Clustered Network-on-chip Monitoring.

[BibT_eX]

Proceedings of the PECCS 2011, 2011

Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems.

[BibT_eX]

Proceedings of the PECCS 2011, 2011

A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication.

[BibT_eX]

[DOI]

Proceedings of the 19th International Euromicro Conference on Parallel, 2011

Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A fault-tolerant and hierarchical routing algorithm for NoC architectures.

[BibT_eX]

[DOI]

Mojtaba Valinataj

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

Q-learning based congestion-aware routing algorithm for on-chip network.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Thermal Analysis of Advanced 3D Stacked Systems.

[BibT_eX]

[DOI]

Kameswar Rao Vaddina

Khalid Latif

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Power-Efficient Inter-Layer Communication Architectures for 3D NoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's.

[BibT_eX]

[DOI]

Kameswar Rao Vaddina

Khalid Latif

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Cluster-based topologies for 3D stacked architectures.

[BibT_eX]

[DOI]

Proceedings of the 8th Conference on Computing Frontiers, 2011

An adaptive fuzzy logic-based routing algorithm for networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

HIBS - Novel inter-layer bus structure for stacked architectures.

[BibT_eX]

[DOI]

Masoud Daneshtalab

Masoumeh Ebrahimi

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Modeling Communication in Multi-Processor Systems-on-Chip Using Modular Connectors.

[BibT_eX]

[DOI]

Leonidas Tsiopoulos

Int. J. Embed. Real Time Commun. Syst., 2010

Current Challenges in Embedded Communication Systems.

[BibT_eX]

[DOI]

Seppo Virtanen

Int. J. Embed. Real Time Commun. Syst., 2010

Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2010

Thermal modelling of 3D multicore systems in a flip-chip package.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing.

[BibT_eX]

[DOI]

Proceedings of the 18th Euromicro Conference on Parallel, 2010

A Low-Latency and Memory-Efficient On-chip Network.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2010, 2010

BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

High-Performance TSV Architecture for 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Input-Output Selection Based Router for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Heap access optimizations for a hardware-accelerated Java virtual machine.

[BibT_eX]

[DOI]

Joonas Tyystjärvi

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Process variation tolerant on-chip communication using receiver and driver reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Monitoring and reconfiguration techniques for power supply variation tolerant on-chip links.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Tree-model based mapping for energy-efficient and low-latency Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs.

[BibT_eX]

[DOI]

Mohammad Hossein Neishaburi

Proceedings of the 7th Conference on Computing Frontiers, 2010

CMIT - A novel cluster-based topology for 3D stacked architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Self-timed thermal sensing and monitoring of multicore systems.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

An efficent dynamic multicast routing protocol for distributing traffic in NOCs.

[BibT_eX]

[DOI]

Masoumeh Ebrahimi

Masoud Daneshtalab

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Area efficient delay-insensitive and differential current sensing on-chip interconnect.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A novel hardware acceleration scheme for java method calls.

[BibT_eX]

[DOI]

Joonas Tyystjärvi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Rigorous Communication Modelling at Transaction Level With Systemc.

[BibT_eX]

Proceedings of the ICSOFT 2008, 2008

2007

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling.

[BibT_eX]

[DOI]

VLSI Design, 2007

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC.

[BibT_eX]

[DOI]

Teijo Lehtonen

VLSI Design, 2007

Power Aware System Refinement.

[BibT_eX]

[DOI]

Johanna Tuominen

Proceedings of the BCS-FACS Refinement Workshop, 2007

Analysis of forward error correction methods for nanoscale networks-on-chip.

[BibT_eX]

[DOI]

Teijo Lehtonen

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

FPGA Prototype of the REALJava Co-Processor.

[BibT_eX]

[DOI]

Joonas Tyystjärvi

Proceedings of the International Symposium on System-on-Chip, 2007

Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Fault Tolerance Analysis of NoC Architectures.

[BibT_eX]

[DOI]

Teijo Lehtonen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Time Aware System Refinement.

[BibT_eX]

[DOI]

Proceedings of the 11th Refinement Workshop, 2006

Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Parallel and Distributed Computing, 2006

Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Formal Modelling of Multiclocked SoC Systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An approach for analysing and improving fault tolerance in radio architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Time Aware Modelling and Analysis of Multiclocked VLSI Systems.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2006

2005

Asynchronous system synthesis.

[BibT_eX]

[DOI]

Marina Waldén

Sci. Comput. Program., 2005

Formal Specification of a Protocol Processor.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

On-chip Debug for an Asynchronous Java Accelerator.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Formal Modelling of Synchronous Hardware Components for System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Towards a Formal Power Estimation Framework for Hardware Systems.

[BibT_eX]

[DOI]

Johanna Tuominen

Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Instruction Folding for an Asynchronous Java Co-Processor.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Reliable Asynchronous Links for SoC.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Modelling and Refinement of an On-Chip Communication Architecture.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2005

2004

Self-timed communication platform for implementing high-performance systems-on-chip.

[BibT_eX]

[DOI]

Integr., 2004

Refinement of on-chip communication channels.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Constituent Elements of a Correctness-Preserving UML Design Approach.

[BibT_eX]

[DOI]

Proceedings of the Integrated Formal Methods, 4th International Conference, 2004

2003

Implementation of a Self-Timed Segmented Bus.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Modeling on-chip communication.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on System-on-Chip, 2003

2002

Interconnect peak current reduction for wavelet array processor using self-timed signaling.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Specification of an Asynchronous On-chip Bus.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods and Software Engineering, 2002

Design with Asynchronously Communicating Components.

[BibT_eX]

[DOI]

Marina Waldén

Proceedings of the Formal Methods for Components and Objects, 2002

2001

Asynchronous interface for locally clocked modules in ULSI systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Formal Pipeline Design.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000

Design of Synchronous Action Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1997

Action Systems in Pipelined Processor Design.

[BibT_eX]

[DOI]