Jude Angelo Ambrose
Affiliations:- University of New South Wales, Sydney, Australia
According to our database1,
Jude Angelo Ambrose
authored at least 46 papers
between 2007 and 2021.
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Bibliography
2021
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks.
ACM Trans. Design Autom. Electr. Syst., 2021
2017
Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors.
IEEE Trans. Computers, 2017
2016
ACM Comput. Surv., 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks.
Proceedings of the 2015 International Conference on Compilers, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study.
CoRR, 2014
Reconfigurable Convolutional Codec for Physical Layer Communication Security Application.
Proceedings of the 2014 IEEE Military Communications Conference, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks.
IET Circuits Devices Syst., 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Variable increment step based reconfigurable interleaver for multimode communication application.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
ACM Trans. Embed. Comput. Syst., 2012
CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Microprocess. Microsystems, 2011
Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks.
IET Comput. Digit. Tech., 2011
Proceedings of the 8th Conference on Computing Frontiers, 2011
Composability and Predictability for Independent Application Development, Verification, and Execution.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010
2009
PhD thesis, 2009
2008
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007