Juanjo Noguera

According to our database, Juanjo Noguera authored at least 37 papers between 1999 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Xilinx First 7nm Device: Versal AI Core (VC1902).

Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, Shankar Lakka, Fu-Hing Ho, Tomai Knopp, Juanjo Noguera, Gaurav Singh, Ralph Wittig

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

2015

Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC.

Daniel Jiménez-González, Carlos Álvarez, Antonio Filgueras, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers

CoRR, 2015

2014

OmpSs@Zynq all-programmable SoC ecosystem.

Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013

Software-programmable digital pre-distortion on the Zynq SoC.

Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq.

Antonio Filgueras, Eduard Gil, Carlos Álvarez, Daniel Jiménez-González, Xavier Martorell, Jan Langer, Juanjo Noguera

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

2011

High-Level Synthesis for FPGAs: From Prototyping to Deployment.

Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Model-Based Approach to Cognitive Radio Design.

Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Linda Doyle

IEEE J. Sel. Areas Commun., 2011

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs.

Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools.

Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera

Proceedings of the Design, Automation and Test in Europe, 2011

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.

Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.

Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt

ACM Trans. Reconfigurable Technol. Syst., 2010

Iris: an architecture for cognitive radio networking testbeds.

Paul D. Sutton, Jörg Lotze, Hicham Lahlou, Suhaib A. Fahmy, Keith E. Nolan, Baris Özgül, Thomas W. Rondeau, Juanjo Noguera, Linda Doyle

IEEE Commun. Mag., 2010

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration.

Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration.

Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs.

Michael Hübner, Diana Göhringer, Juanjo Noguera, Jürgen Becker

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds.

Paul D. Sutton, Jörg Lotze, Hicham Lahlou, Baris Özgül, Suhaib A. Fahmy, Keith E. Nolan, Juanjo Noguera, Linda E. Doyle

Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010

2009

Development Framework for Implementing FPGA-Based Cognitive Network Nodes.

Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris Özgül, Linda Doyle, Robert Esser

Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Generic Software Framework for Adaptive Applications on FPGAs.

Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser

Proceedings of the FCCM 2009, 2009

2008

Towards Novel Approaches in Design Automation for FPGA Power Optimization.

Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Power Reduction in Network Equipment through Adaptive Partial Reconfiguration.

Juanjo Noguera, Irwin O. Kennedy

Proceedings of the FPL 2007, 2007

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.

Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera

Proceedings of the 44th Design Automation Conference, 2007

2006

System-level power-performance tradeoffs for reconfigurable computing.

Juanjo Noguera, Rosa M. Badia

IEEE Trans. Very Large Scale Integr. Syst., 2006

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration.

Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Software-friendly HW/SW co-simulation: an industrial case study.

Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures.

Juanjo Noguera, Rosa M. Badia

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures.

Zexin Pan, Juanjo Noguera, B. Earl Wells

Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004

Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling.

Juanjo Noguera, Rosa M. Badia

ACM Trans. Embed. Comput. Syst., 2004

Power-performance trade-offs for reconfigurable computing.

Juanjo Noguera, Rosa M. Badia

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.

Juanjo Noguera, Rosa M. Badia

Proceedings of the International Conference on Compilers, 2003

2002

HW/SW codesign techniques for dynamically reconfigurable architectures.

Juanjo Noguera, Rosa M. Badia

IEEE Trans. Very Large Scale Integr. Syst., 2002

Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures.

Juanjo Noguera, Rosa M. Badia

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001

A HW/SW partitioning algorithm for dynamically reconfigurable architectures.

Juanjo Noguera, Rosa M. Badia

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures.

Juanjo Noguera, Rosa M. Badia

Proceedings of the 13th International Symposium on System Synthesis, 2000

Modelling and Performance Evaluation of a National Scale Switchless Based Network.

Josep Solé-Pareta, Davide Careglio, Salvatore Spadaro, Jaume Masip-Torné, Juanjo Noguera, Gabriel Junyent

Proceedings of the Next Generation Networks, 2000

Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers.

Juanjo Noguera, Rosa M. Badia

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation.

Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation.

Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta

Proceedings of the 25th EUROMICRO '99 Conference, 1999