Juang-Ying Chueh

According to our database, Juang-Ying Chueh authored at least 9 papers between 2004 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.

Nicky Lu, Chun Shiah, Juang-Ying Chueh, Bor-Doou Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, Chia-Wei Chang, Tzung-Shen Chen

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2013

Efficient standard cell abutment checker.

Juang-Ying Chueh, Chuck Tung

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2007

Energy-Efficient GHz-Class Charge-Recovery Logic.

Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou

IEEE J. Solid State Circuits, 2007

2006

A 1.1ghz charge-recovery logic.

Visvesh S. Sathe, Juang-Ying Chueh, Marios Papaefthymio

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading.

Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Two-Phase Resonant Clock Distribution.

Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Fast, efficient, recovering, and irreversible.

Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou

Proceedings of the Second Conference on Computing Frontiers, 2005

2004

Experimental Evaluation of Resonant Clock Distribution.

Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Empirical evaluation of timing and power in resonant clock distribution.

Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004