Juan Salamanca

According to our database, Juan Salamanca authored at least 14 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Using hardware-transactional-memory support to implement speculative task execution.

Juan Salamanca, Alexandro Baldassin

J. Parallel Distributed Comput., 2024

2023

Evaluating the Performance of Speculative DOACROSS Loop Parallelization with taskloop.

Juan Salamanca, Alexandro Baldassin

CoRR, 2023

How to Efficiently Parallelize Irregular DOACROSS Loops Using Fine Granularity and OpenMP Tasks: The SPEC mcf Case.

Juan Salamanca, Alexandro Baldassin

Proceedings of the OpenMP: Advanced Task-Based, Device and Compiler Programming, 2023

2022

Using Off-the-Shelf Hardware Transactional Memory to Implement Speculative While in OpenMP.

Juan Salamanca, Alexandro Baldassin

Proceedings of the OpenMP in a Modern World: From Multi-device Support to Meta Programming, 2022

Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory.

Juan Salamanca

Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022

2021

Improving Speculative taskloop in Hardware Transactional Memory.

Juan Salamanca, Alexandro Baldassin

Proceedings of the OpenMP: Enabling Massive Node-Level Parallelism, 2021

2020

Using Hardware Transactional Memory to Implement Speculative Privatization in OpenMP.

Juan Salamanca, Alexandro Baldassin

Proceedings of the Languages and Compilers for Parallel Computing, 2020

2019

A Proposal for Supporting Speculation in the OpenMP taskloop Construct.

Juan Salamanca, Alexandro Baldassin

Proceedings of the OpenMP: Conquering the Full Hardware Spectrum, 2019

2018

Using Hardware-Transactional-Memory Support to Implement Thread-Level Speculation.

Juan Salamanca, José Nelson Amaral, Guido Araujo

IEEE Trans. Parallel Distributed Syst., 2018

DOACROSS Parallelization Based on Component Annotation and Loop-Carried Probability.

Luis Mattos, Divino Cesar S. Lucas, Juan Salamanca, Joao P. L. de Carvalho, Márcio Machado Pereira, Guido Araujo

Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

2017

Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories.

Juan Salamanca, José Nelson Amaral, Guido Araujo

Proceedings of the Euro-Par 2017: Parallel Processing - 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28, 2017

2016

Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories.

Juan Salamanca, José Nelson Amaral, Guido Araujo

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

2015

Using Hardware Transactional Memory to Enable Speculative Trace Optimization.

Juan Salamanca, José Nelson Amaral, Guido Araujo

Proceedings of the 2015 International Symposium on Computer Architecture and High Performance Computing Workshops, 2015

2014

Loop-Carried Dependence Verification in OpenMP.

Juan Salamanca, Luis Mattos, Guido Araujo

Proceedings of the Using and Improving OpenMP for Devices, Tasks, and More, 2014