Juan P. Oliver

Orcid: 0000-0001-7098-674X

According to our database1, Juan P. Oliver authored at least 16 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Tuning high-level synthesis SpMV kernels in Alveo FPGAs.
Microprocess. Microsystems, 2024

Low-Power Wireless Sensor Network for Real-Time Indoor Air Quality Monitoring with CO2 Sensors.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2022
Time-Power-Energy Balance of blas Kernels in Modern fpgas.
Proceedings of the High Performance Computing - 9th Latin American Conference, 2022

2021
Energy-efficient algebra kernels in FPGA for High Performance Computing.
J. Comput. Sci. Technol., 2021

Unleashing the computational power of FPGAs to efficiently perform SPMV operation.
Proceedings of the 40th International Conference of the Chilean Computer Science Society, 2021

2020
Understanding the Performance of Elementary NLA Kernels in FPGAs.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
A Framework to Compare Estimated and Measured Power Consumption on FPGAs.
J. Low Power Electron., 2019

2018
Wireless EEG System Achieving High Throughput and Reduced Energy Consumption Through Lossless and Near-Lossless Compression.
IEEE Trans. Biomed. Circuits Syst., 2018

A 64-channel wireless EEG recording system for wearable applications.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
A Low Cost System for Self Measurements of Power Consumption in Field Programmable Gate Arrays.
J. Low Power Electron., 2017

2016
Wearable EEG via lossless compression.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2013
Self-Reconfigurable Constant Multiplier for FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2013

Tracking the pipelining-power rule along the FPGA technical literature.
Proceedings of the 10th FPGAworld Conference, 2013

2009
Lab at Home: Hardware Kits for a Digital Design Lab.
IEEE Trans. Educ., 2009

2005
Hardware Lab at Home Possible with Ultra Low Cost Boards.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005


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