Juan Carlos Baraza

Orcid: 0000-0001-7692-2309

Affiliations:
  • Polytechnic University of Valencia, Spain


According to our database1, Juan Carlos Baraza authored at least 31 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays.
IEEE Access, 2024

2019
Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection.
IEEE Access, 2019

2018
Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes.
Proceedings of the 8th Latin-American Symposium on Dependable Computing, 2018

2016
Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System.
IEEE Trans. Reliab., 2016

Ultrafast Error Correction Codes for Double Error Detection/Correction.
Proceedings of the 12th European Dependable Computing Conference, 2016

2015
Ultrafast Single Error Correction Codes for Protecting Processor Registers.
Proceedings of the 11th European Dependable Computing Conference, 2015

2014
Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor.
IEEE Trans. Reliab., 2014

Modified Hamming Codes to Enhance Short Burst Error Detection in Semiconductor Memories (Short Paper).
Proceedings of the 2014 Tenth European Dependable Computing Conference, 2014

2013
Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels.
Proceedings of the Computer Safety, Reliability, and Security, 2013

Defining a Representative and Low Cost Fault Model Set for Intermittent Faults in Microprocessor Buses.
Proceedings of the Sixth Latin-American Symposium on Dependable Computing, 2013

Using Interleaving to Avoid the Effects of Multiple Adjacent Faults in On-Chip Interconnection Lines.
Proceedings of the Dependable Computing - 14th European Workshop, 2013

Improving the Transfer of Safety and Security Competences to Industry: The RISKY Approach.
Proceedings of the Dependable Computing - 14th European Workshop, 2013

2012
Studying the effects of intermittent faults on a microcontroller.
Microelectron. Reliab., 2012

Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection.
IEEE Des. Test, 2012

2010
Searching Representative and Low Cost Fault Models for Intermittent Faults in Microcontrollers: A Case Study.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

Experimental validation of a fault tolerant microcomputer system against intermittent faults.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

2008
Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Injecting intermittent faults for the dependability validation of commercial microcontrollers.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Analysis of the influence of intermittent faults in a microcontroller.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2005
Improvement of fault injection techniques based on VHDL code modification.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Impact of Faults in Combinational Logic of Commercial Microcontrollers.
Proceedings of the Dependable Computing, 2005

2004
Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2003
Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system.
Microelectron. J., 2003

2002
A prototype of a VHDL-based fault injection tool: description and application.
J. Syst. Archit., 2002

Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

2001
A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection Techniques.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Comparison and Application of Different VHDL-Based Fault Injection Techniques.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

A Prototype of a VHDL-Based Fault Injection Tool.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System.
Proceedings of the Dependable Computing, 1999

1998
Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System.
Proceedings of the 24th EUROMICRO '98 Conference, 1998


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