Juan A. Michell

J. Signal Process. Syst., 2013

A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC.

[BibT_eX]

[DOI]

Miguel A. Manzano

J. Signal Process. Syst., 2013

2011

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC.

[BibT_eX]

[DOI]

Signal Process. Image Commun., 2011

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC.

[BibT_eX]

[DOI]

José M. Solana

Signal Process. Image Commun., 2011

2006

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

2005

Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2005

High throughput 2D DCT/IDCT processor for video coding.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Image Processing, 2005

2003

Parallel-pipelined architecture for 2-D ICT VLSI implementation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Image Processing, 2003

1999

VLSI configurable delay commutator for a pipeline split radix FFT architecture.

[BibT_eX]

[DOI]

Jesús García

IEEE Trans. Signal Process., 1999

1998

Memory efficient programmable processor chip for inverse Haar transform.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1998

1995

Fully pipelined TSPC barrel shifter for high-speed applications.

[BibT_eX]

[DOI]

R. Pereira