Józef Kulisz

According to our database, Józef Kulisz authored at least 9 papers between 2005 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs.

Marcin Kubica, Dariusz Kania, Józef Kulisz

IEEE Access, 2019

2016

An IEC 61131-3-based PLC implemented by means of an FPGA.

Miroslaw Chmiel, Józef Kulisz, Robert Czerwinski, A. Krzyzyk, Marcin Rosol, Patryk Smolarek

Microprocess. Microsystems, 2016

2013

An IP-Core Generator for Circuits Performing Arithmetic Multiplication.

Józef Kulisz, Jerzy Mikucki

Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013

Generating Time Intervals in Programmable Logic Controllers.

Józef Kulisz, Miroslaw Chmiel, Andrzej Malcher

Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, 2013

2010

A PC-based object simulator for supporting PLC software development.

Józef Kulisz, Robert Czerwinski, Jan Mocha, Miroslaw Chmiel

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

2009

State machine description oriented towards effective usage of vendor-independent synthesis tools.

Robert Czerwinski, Józef Kulisz

Proceedings of the 9th IFAC Workshop on Programmable Devices and Embedded Systems, 2009

2007

Logic synthesis for PAL-based CPLD-s based on two-stage decomposition.

Dariusz Kania, Józef Kulisz

J. Syst. Softw., 2007

2005

Decomposition of Multi-Output Functions for CPLDs.

Dariusz Kania, Adam Milik, Józef Kulisz

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs.

Dariusz Kania, Józef Kulisz, Adam Milik

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005