Joycee Mekie

Orcid: 0000-0001-9646-1941

According to our database1, Joycee Mekie authored at least 63 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy.
ACM Trans. Archit. Code Optim., June, 2023

Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Fast and Robust Sense Amplifier for Digital In Memory Computing.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Process Variation Resilient Current-Domain Analog In Memory Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Analysis of Quantization Across DNN Accelerator Architecture Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Power-Efficient Approximate Multipliers Leveraging Hybrid CMOS-Memristor Paradigm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A 10T, 0.22fJ/Bit/Search Mixed-V<sub>T</sub> Pseudo Precharge-Free Content Addressable Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms.
CoRR, 2022

Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

FastMem: A Fast Architecture-aware Memory Layout Design.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

RHSCC-16T: Radiation Hardened Sextuple Cross Coupled Robust SRAM Design for Radiation Prone Environments.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Analysis of Worst-Case Data Dependent Temporal Approximation in Floating Point Units.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Fixed-Posit: A Floating-Point Representation for Error-Resilient Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Learning by Cheating : An End-to-End Zero Shot Framework for Autonomous Drone Navigation.
CoRR, 2021

HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy.
CoRR, 2021

FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Energy and Error Analysis Framework for Approximate Computing in Mobile Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Tunable Inexact Subtracters for Division in Image Processing Applications.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Low-Voltage Split Memory Architecture for Binary Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

PANE: Pluggable Asynchronous Network-on-Chip Simulator.
ACM J. Emerg. Technol. Comput. Syst., 2019

Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder.
IET Comput. Digit. Tech., 2019

Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-Flop.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Quality Tunable Approximate Adder for Low Energy Image Processing Applications.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

SEDA - Single Exact Dual Approximate Adders for Approximate Processors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Should We Code Differently When Using Approximate Circuits?
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
Impact of Variations on Synchronizer Performance: An Experimental Study.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2016
Fault tolerant tactile sensor arrays for prosthesis.
Proceedings of the 6th IEEE International Conference on Biomedical Robotics and Biomechatronics, 2016

2014
Tutorial T7B: Network on Chips - The Journey Overview.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked Systems.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2006
Reasoning about synchronization in GALS systems.
Formal Methods Syst. Des., 2006

Interface Design for Rationally Clocked GALS Systems.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2004
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004


  Loading...