Joy Alinda Reyes
According to our database1,
Joy Alinda Reyes
authored at least 4 papers
between 2008 and 2010.
Collaborative distances:
Collaborative distances:
Timeline
2008
2009
2010
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1
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2
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2010
A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design.
Proceedings of the 12th UKSim, 2010
Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL.
Proceedings of the 12th UKSim, 2010
2008
Analysis of Different AMBA-Based Bus Interconnection Schemes for ARM7 Multicore Environment.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2008
DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008