Jouni Isoaho

Orcid: 0000-0002-5789-3992

According to our database1, Jouni Isoaho authored at least 103 papers between 1992 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Defining and Modeling Forced Trust and Its Dependencies in Smart Environments.
IEEE Access, 2024

2023
Self-Aware Cybersecurity Architecture for Autonomous Vehicles: Security through System-Level Accountability.
Sensors, October, 2023

Toward Autonomic Internet of Things: Recent Advances, Evaluation Criteria, and Future Research Directions.
IEEE Internet Things J., August, 2023

2022
Quantum Key Distribution: Modeling and Simulation through BB84 Protocol Using Python3.
Sensors, 2022

2021
From information seeking to information avoidance: Understanding the health information behavior during a global health crisis.
Inf. Process. Manag., 2021


Conceptual design of a trust model for perceptual sensor data of autonomous vehicles.
Proceedings of the 12th International Conference on Ambient Systems, 2021

Understanding Dynamics of Initial Trust and its Antecedents in Password Managers Adoption Intention among Young Adults.
Proceedings of the 12th International Conference on Ambient Systems, 2021

2020
The Impact of Perceived Security on Intention to use E-Learning Among Students.
Proceedings of the 20th IEEE International Conference on Advanced Learning Technologies, 2020

Cybersecurity Education and Skills: Exploring Students' Perceptions, Preferences and Performance in a Blended Learning Initiative.
Proceedings of the 2020 IEEE Global Engineering Education Conference, 2020

2019
Predicting Students' Security Behavior Using Information-Motivation-Behavioral Skills Model.
Proceedings of the ICT Systems Security and Privacy Protection, 2019

Conceptual Security System Design for Mobile Platforms Based on Human Nervous System.
Proceedings of the Innovative Mobile and Internet Services in Ubiquitous Computing, 2019

SAMoC: Self-aware Access Monitoring and Controlling Framework for Android.
Proceedings of the Information and Communication Technology for Development for Africa, 2019

Factors Affecting Security Behavior of Kenyan Students: An Integration of Protection Motivation Theory and Theory of Planned Behavior.
Proceedings of the 2019 IEEE AFRICON, Accra, Ghana, September 25-27, 2019, 2019

2018
Hybrid Internal Anomaly Detection System for IoT: Reactive Nodes with Cross-Layer Operation.
Secur. Commun. Networks, 2018

CoDRA: Context-based dynamically reconfigurable access control system for android.
J. Netw. Comput. Appl., 2018

Low-Latency Approach for Secure ECG Feature Based Cryptographic Key Generation.
IEEE Access, 2018

Towards Human Bio-Inspired Defence Mechanism for Cyber Security.
Proceedings of the 2018 IEEE Security and Privacy Workshops, 2018

Performance Analysis of End-to-End Security Schemes in Healthcare IoT.
Proceedings of the 9th International Conference on Ambient Systems, 2018

2017
Towards Self-aware Approach for Mobile Devices Security.
Proceedings of the Computer Network Security, 2017

Self-aware Access Control System for Android.
Proceedings of the Innovative Mobile and Internet Services in Ubiquitous Computing, 2017

Cryptographic key generation using ECG signal.
Proceedings of the 14th IEEE Annual Consumer Communications & Networking Conference, 2017

2016
End-to-end security scheme for mobility enabled healthcare Internet of Things.
Future Gener. Comput. Syst., 2016

Dimensions of Internet Use and Threat Sensitivity: An Exploratory Study among Students of Higher Education.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

Distributed internal anomaly detection system for Internet-of-Things.
Proceedings of the 13th IEEE Annual Consumer Communications & Networking Conference, 2016

2015
Observations on Genderwise Differences among University Students in Information Security Awareness.
Int. J. Inf. Secur. Priv., 2015

Information Security Awareness in Educational Institution: An Analysis of Students' Individual Factors.
Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

A taxonomy of perceived information security and privacy threats among IT security students.
Proceedings of the 10th International Conference for Internet Technology and Secured Transactions, 2015

SEA: A Secure and Efficient Authentication and Authorization Architecture for IoT-Based Healthcare Using Smart Gateways.
Proceedings of the 6th International Conference on Ambient Systems, 2015

Session Resumption-Based End-to-End Security for Healthcare Internet-of-Things.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014
Energy-aware adaptive security management for wireless sensor networks.
Proceedings of the Proceeding of IEEE International Symposium on a World of Wireless, 2014

An Elliptic Curve-based Mutual Authentication Scheme for RFID Implant Systems.
Proceedings of the 5th International Conference on Ambient Systems, 2014

2013
Runtime adaptation key to extend lifetime of wireless sensor networks.
Proceedings of the 15th IEEE International Conference on Communication Technology, 2013

2012
Modeling of Energy Dissipation in RLC Current-Mode Signaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Incubator Platform for Multidisciplinary Innovation in Research and Education.
Int. J. Knowl. Soc. Res., 2012

Survey of Self-Adaptive NoCs with Energy-Efficiency and Dependability.
Int. J. Embed. Real Time Commun. Syst., 2012

Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses.
IET Comput. Digit. Tech., 2012

Coarse and fine-grained monitoring and reconfiguration for energy-efficient NoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

HLS-DoNoC: High-level simulator for dynamically organizational NoCs.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.
IET Circuits Devices Syst., 2011

Hybrid Trust Model for Internet Routing
CoRR, 2011

Hierarchical Agent Monitoring Design Platform - Towards Self-aware and Adaptive Embedded Systems.
Proceedings of the PECCS 2011, 2011

2010
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip.
ACM Trans. Embed. Comput. Syst., 2010

Interconnection alternatives for hierarchical monitoring communication in parallel SoCs.
Microprocess. Microsystems, 2010

Current Challenges in Embedded Communication Systems.
Int. J. Embed. Real Time Commun. Syst., 2010

Hierarchical Agent Monitored Parallel On-Chip System: A Novel Design Paradigm and its Formal Specification.
Int. J. Embed. Real Time Commun. Syst., 2010

Process variation tolerant on-chip communication using receiver and driver reconfiguration.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Monitoring and reconfiguration techniques for power supply variation tolerant on-chip links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A software defined approach for common baseband processing.
J. Syst. Archit., 2008

Objectives for New Error Criteria for Mobile Broadcasting of Streaming Audiovisual Services.
EURASIP J. Adv. Signal Process., 2008

Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Area efficient delay-insensitive and differential current sensing on-chip interconnect.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Utterance-level normalization for relative articulation rate analysis.
Proceedings of the 9th Annual Conference of the International Speech Communication Association, 2008

Correlation of utterance length and segmental duration in Finnish is questionable.
Proceedings of the 9th Annual Conference of the International Speech Communication Association, 2008

2007
High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling.
VLSI Design, 2007

Utterance-Initial Duration of Finnish Non-Plosive Consonants.
Proceedings of the 16th Nordic Conference of Computational Linguistics, 2007

Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Analytical model for crosstalk and intersymbol interference in point-to-point buses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip.
Proceedings of the International Symposium on System-on-Chip, 2006

Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects.
Proceedings of the International Symposium on System-on-Chip, 2006

Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An approach for analysing and improving fault tolerance in radio architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Implementing a Rule-Based Speech Synthesizer on a Mobile Platform.
Proceedings of the Advances in Natural Language Processing, 2006

Segmental Duration in Utterance-Initial Environment: Evidence from Finnish Speech Corpora.
Proceedings of the Advances in Natural Language Processing, 2006

The Vowel Game: Continuous Real-Time Visualization for Pronunciation Learning with Vowel Charts.
Proceedings of the Advances in Natural Language Processing, 2006

2005
Tuning a Protocol Processor Architecture Towards DSP Operations.
Proceedings of the Embedded Computer Systems: Architectures, 2005

The SoC-Mobinet Model in System-on-Chip Education.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Reliable Asynchronous Links for SoC.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Case study of interconnect analysis for standing wave oscillator design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Modelling and Refinement of an On-Chip Communication Architecture.
Proceedings of the Formal Methods and Software Engineering, 2005

Highly Automated FPGA Synthesis of Application-Specific Protocol Processors.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Self-timed communication platform for implementing high-performance systems-on-chip.
Integr., 2004

Refinement of on-chip communication channels.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

SoC-Mobinet, R&D and education in system-on-chip design.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Analyses of signaling techniques for self-timed systems.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003
Self-Timed Approach for Reducing On-Chip Switching Noise.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Estimation of Crosstalk Noise for On-Chip Buses.
Proceedings of the Integrated Circuit and System Design, 2003

Block-wise Extraction of Rent's Exponents for an Extensible Processor.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Software for the Changing E-Business.
Proceedings of the Digital Communities in a Networked Society: eCommerce, 2003

2002
Interconnection of autonomous error-tolerant cells.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Interconnect peak current reduction for wavelet array processor using self-timed signaling.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
High-speed serial communication with error correction using 0.25 um CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Asynchronous interface for locally clocked modules in ULSI systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A multiplier-free fixed-task digital CNN array for video segmentation system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Design and Implementation of Viterbi Decoder with FPGAs.
J. VLSI Signal Process., 1999

Design of a super-pipelined Viterbi decoder.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
BOAR: an advanced HW/SW coemulation environment for DSP system development.
Microprocess. Microsystems, 1997

System oriented VLSI curriculum at KTH.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

1996
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1994
An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques.
Proceedings of the Field-Programmable Logic, 1994

1993
DSP system integration and prototyping with FPGAS.
J. VLSI Signal Process., 1993

1992
Technologies and Utilization fo Field Programmable Gate Arrays.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992


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