Joshua Mack
Orcid: 0000-0003-1066-5578
According to our database1,
Joshua Mack
authored at least 23 papers
between 2015 and 2024.
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Bibliography
2024
IEEE Des. Test, February, 2024
IEEE Trans. Computers, January, 2024
An Ecosystem for Evaluating Domain-Specific System on Chip (DSSoC) Devices: Productive Application Deployment and Scheduling Perspectives.
PhD thesis, 2024
Proceedings of the Neuro Inspired Computational Elements Conference, 2024
A Runtime Manager Integrated Emulation Environment for Heterogeneous SoC Design with RISC-V Cores.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
2023
ACM Trans. Embed. Comput. Syst., March, 2023
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
2022
Performant, Multi-Objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices.
IEEE Trans. Parallel Distributed Syst., 2022
CoRR, 2022
A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC.
Proceedings of the IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2022
Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2020
IEEE Trans. Computers, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
FPGA Based High-Throughput Real-Time Feature Extraction for Modulation Classification.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2019
CoRR, 2019
Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019
Proceedings of the 16th IEEE/ACS International Conference on Computer Systems and Applications, 2019
2016
CoRR, 2016
2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015