Joshua Liang

According to our database, Joshua Liang authored at least 13 papers between 2010 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators.

Yi Fan Zhang, Joshua Liang, Tony Chan Carusone

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2019

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.

Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2018

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2018

2017

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS.

Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

IEEE J. Solid State Circuits, 2017

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS.

Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Jitter injection for on-chip jitter measurement in PI-based CDRs.

Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2015

A 3x blind ADC-based CDR for a 20 dB loss channel.

Mohammad Sadegh Jalali, Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs.

Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE J. Solid State Circuits, 2015

2014

On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs.

Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

2013

A Blind Baud-Rate ADC-Based CDR.

Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

IEEE J. Solid State Circuits, 2013

2010

A frequency-scalable 15-bit incremental ADC for low power sensor applications.

Joshua Liang, David A. Johns

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010