Josh Yang

According to our database, Josh Yang authored at least 7 papers between 2003 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Analysis and characterization of process/layout impacts on the performance of high-speed analog circuits.

Long Zhao, Feng Zou, Josh Yang, Tianshen Tang, Yuhua Cheng

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2006

Fast detection of data retention faults and other SRAM cell open defects.

Josh Yang, Baosheng Wang, Yuejian Wu, André Ivanov

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005

SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.

Baosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A retention-aware test power model for embedded SRAM.

Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Reducing Embedded SRAM Test Time under Redundancy Constraints.

Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.

Josh Yang, Baosheng Wang, André Ivanov

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Reducing Test Time of Embedded SRAMs.

Baosheng Wang, Josh Yang, André Ivanov

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003