Joseph T. Kennedy
Affiliations:- Intel Labs, Hillsboro, OR, USA
According to our database1,
Joseph T. Kennedy
authored at least 23 papers
between 2003 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
18.2 A 4x64Gb/s NRZ 1.3pJ/b Co-Packaged and Fiber-Terminated 4-Ch VCSEL-Based Optical Transmitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2018
A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2014
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.
IEEE J. Solid State Circuits, 2005
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew.
IEEE J. Solid State Circuits, 2005
2003
IEEE J. Solid State Circuits, 2003