Joseph Petolino

According to our database, Joseph Petolino authored at least 4 papers between 1988 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency.

Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino

IEEE J. Solid State Circuits, 1998

1994

microSPARC^TM: A Case Study of Scan-Based Debug.

Kalon Holdbrook, Sunil Joshi, Samir Mitra, Joe Petolino, Renu Raman, Michelle Wong

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1990

Implementing Sparc in ECL.

Emil W. Brown, Anant Agrawal, Trevor Creary, Michael F. Klein, Dave Murata, Joseph Petolino

IEEE Micro, 1990

1988

Design Considerations for a Bipolar Implementation of SPARC.

Anant Agrawal, Eric W. Brown, Joe Petolino, James R. Peterson

Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988