Josep Rius

According to our database, Josep Rius authored at least 21 papers between 1992 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors.

Josep Rius

IEEE Trans. Very Large Scale Integr. Syst., 2015

2013

IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption.

Josep Rius

IEEE Trans. Very Large Scale Integr. Syst., 2013

2010

A method for detecting resistive opens in buses.

Josep Rius

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Two-dimensional communication of networked devices through a single conductive surface.

Josep Rius

Proceedings of the Seventh International Conference on Networked Sensing Systems, 2010

A single conductive surface as communication media for networked devices.

Josep Rius

Proceedings of the 5th International ICST Conference on Body Area Networks, 2010

2009

Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors.

Josep Rius, Maurice Meijer

IEEE J. Solid State Circuits, 2009

Analysis of the extra delay on interconnects caused by resistive opens and shorts.

Pablo Maqueda, Josep Rius

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.

Josep Rius, Luis Elvira Villagra, Maurice Meijer

Proceedings of the 14th IEEE European Test Symposium, 2009

2006

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.

Josep Rius, Maurice Meijer, José Pineda de Gyvez

J. Low Power Electron., 2006

2004

Built-in current sensor for ΔI_DDQ testing.

Josep Rius Vázquez, José Pineda de Gyvez

IEEE J. Solid State Circuits, 2004

Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs.

Josep Rius Vázquez, José Pineda de Gyvez

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

BIST Technique by Equally Spaced Test Vector Sequences.

Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Power Supply Noise Monitor for Signal Integrity Faults.

Josep Rius Vázquez, José Pineda de Gyvez

Proceedings of the 2004 Design, 2004

2003

Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.

Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez

Proceedings of the Integrated Circuit and System Design, 2003

On the selection of efficient arithmetic additive test pattern generators [logic test].

Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras

Proceedings of the 8th European Test Workshop, 2003

2002

Comparison of IDDQ Testing and Very-Low Voltage Testing.

Bram Kruseman, Stefan van den Oetelaar, Josep Rius

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999

Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.

Josep Rius, Joan Figueras

Proceedings of the 1999 Design, 1999

1998

IDDQ testing: state of the art and future trends.

Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras

Integr., 1998

1996

Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.

Josep Rius, Joan Figueras

J. Electron. Test., 1996

1995

Detecting I_DDQ defective CMOS circuits by depowering.

Josep Rius, Joan Figueras

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1992

Proportional BIC sensor for current testing.

Josep Rius, Joan Figueras

J. Electron. Test., 1992