Josep M. Codina

According to our database, Josep M. Codina authored at least 18 papers between 2001 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units.

Enric Gibert, Raúl Martínez, Carlos Madriles, Josep M. Codina

IEEE Comput. Archit. Lett., 2015

2012

A HW/SW Co-designed Programmable Functional Unit.

Abhishek Deb, Josep M. Codina, Antonio González

IEEE Comput. Archit. Lett., 2012

2011

A Power-Efficient Co-designed Out-of-Order Processor.

Abhishek Deb, Josep M. Codina, Antonio González

Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion.

Abhishek Deb, Josep M. Codina, Antonio González

Proceedings of the 8th Conference on Computing Frontiers, 2011

A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit.

Abhishek Deb, Josep M. Codina, Antonio González

Proceedings of the 15th Workshop on Interaction between Compilers and Computer Architectures, 2011

2009

AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures.

Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli

IEEE Trans. Computers, 2009

Boosting single-thread performance in multi-core systems through fine-grain multi-threading.

Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading.

Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González

Proceedings of the PACT 2009, 2009

2008

A software-hardware hybrid steering mechanism for clustered microarchitectures.

Qiong Cai, Josep M. Codina, José González, Antonio González

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

Virtual Cluster Scheduling Through the Scheduling Graph.

Josep M. Codina, F. Jesús Sánchez, Antonio González

Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

Heterogeneous Clustered VLIW Microarchitectures.

Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli

Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2005

Demystifying on-the-fly spill code.

Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli

Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

2004

Removing communications in clustered microarchitectures through instruction replication.

Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli

ACM Trans. Archit. Code Optim., 2004

2003

Instruction Replication for Clustered Microarchitectures.

Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

2002

A comparative study of modulo scheduling techniques.

Josep M. Codina, Josep Llosa, Antonio González

Proceedings of the 16th international conference on Supercomputing, 2002

Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning.

Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli

Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001

Graph-partitioning based instruction scheduling for clustered processors.

Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors.

Josep M. Codina, F. Jesús Sánchez, Antonio González

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001