Josef Schmid

Orcid: 0000-0003-2914-1547

According to our database1, Josef Schmid authored at least 12 papers between 1986 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Learning-Based Quality of Service Prediction in Cellular Vehicle Communication
PhD thesis, 2022

A Survey on Client Throughput Prediction Algorithms in Wired and Wireless Networks.
ACM Comput. Surv., 2022

2021
Integration of a RTT Prediction into a Multi-path Communication Gateway.
Proceedings of the Computer Safety, Reliability, and Security. SAFECOMP 2021 Workshops, 2021

Analysis and evaluation of the communication requirements for remote operating an automated bus in rural areas.
Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021


2019
A Comparison of AI-Based Throughput Prediction for Cellular Vehicle-To-Server Communication.
Proceedings of the 15th International Wireless Communications & Mobile Computing Conference, 2019

A Deep Learning Approach for Location Independent Throughput Prediction.
Proceedings of the 2019 IEEE International Conference on Connected Vehicles and Expo, 2019

2018
Analysing communication requirements for crowd sourced backend generation of HD Maps used in automated driving.
Proceedings of the 2018 IEEE Vehicular Networking Conference, 2018

Passive monitoring and geo-based prediction of mobile network vehicle-to-server communication.
Proceedings of the 14th International Wireless Communications & Mobile Computing Conference, 2018

2001
Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

1999
Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1986
On the IC architecture and design of a 2 µm CMOS 8 MIPS digital signal processor with parallel processing capability: The PCB5010/5011.
Proceedings of the IEEE International Conference on Acoustics, 1986


  Loading...