Josef Angermeier

According to our database, Josef Angermeier authored at least 21 papers between 2007 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Concepts and Algorithms to Increase the Efficiency and Reliability of Reconfigurable Computers.

Josef Angermeier

PhD thesis, 2013

2012

Dynamic Defragmentation of Reconfigurable Devices.

Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich

ACM Trans. Reconfigurable Technol. Syst., 2012

Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures.

Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich

Int. J. Reconfigurable Comput., 2012

2011

Bitonic Sorting on Dynamically Reconfigurable Architectures.

Josef Angermeier, Eugen Sibirko, Rolf Wanka, Jürgen Teich

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

An FPGA implementation of a threat-based strategy for Connect6.

Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Runtime stress-aware replica placement on reconfigurable devices under safety constraints.

Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Stress-Aware Module Placement on Reconfigurable Devices.

Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

No-Break Dynamic Defragmentation of Reconfigurable

Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich

CoRR, 2010

Maintaining Virtual Areas on FPGAs using Strip Packing with Delays

Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich

CoRR, 2010

Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures.

Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Virtual area management: Multitasking on dynamically partially reconfigurable devices.

Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform.

Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich

Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices.

Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen

Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010

2009

General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems.

Josef Angermeier, Abdulazim Amouri, Jürgen Teich

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Co-design Architecture and Implementation for Point-Based Rendering on FPGAs.

Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich

Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads.

Josef Angermeier, Jürgen Teich

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

No-break dynamic defragmentation of reconfigurable devices.

Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich

Proceedings of the FPL 2008, 2008

A comparison of embedded reconfigurable video-processing architectures.

Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich

Proceedings of the FPL 2008, 2008

Fine grain reconfigurable architectures.

Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker

Proceedings of the FPL 2008, 2008

Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.

Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens).

Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen

it Inf. Technol., 2007