José V. Busquets-Mataix
Orcid: 0000-0003-2949-502X
According to our database1,
José V. Busquets-Mataix
authored at least 14 papers
between 1995 and 2019.
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Bibliography
2019
J. Supercomput., 2019
2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
2005
Proceedings of the Embedded Software and Systems, Second International Conference, 2005
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison.
Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS 2005), 2005
2003
Proceedings of the Real-Time and Embedded Computing Systems and Applications, 2003
2000
Techniques to increase the schedulable utilization of cache-based preemptive real-time systems.
J. Syst. Archit., 2000
1999
Microprocess. Microsystems, 1999
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System.
Proceedings of the Dependable Computing, 1999
1998
Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
1997
Proceedings of the Ninth Euromicro Workshop on Real-Time Systems, 1997
1996
Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems.
Proceedings of the Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30, 1996
Adding instruction cache effect to schedulability analysis of preemptive real-time systems.
Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium, 1996
Adding Instruction Cache Effect to an Exact Schedulability Analysis of Preemptive Real-Time Systems.
Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996
1995
Proceedings of the 2nd International Workshop on Real-Time Computing Systems and Applications, October 25, 1995