José T. de Sousa
Orcid: 0000-0001-7525-7546
According to our database1,
José T. de Sousa
authored at least 42 papers
between 1991 and 2024.
Collaborative distances:
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Bibliography
2024
PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes.
Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024
2023
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units.
ACM Trans. Reconfigurable Technol. Syst., March, 2023
2022
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022
2021
IEEE Access, 2021
2020
A fast and scalable architecture to run convolutional neural networks in low density FPGAs.
Microprocess. Microsystems, 2020
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs.
IEEE Access, 2020
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
2016
Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2008
Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction.
IET Comput. Digit. Tech., 2008
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
2005
J. Autom. Reason., 2005
A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
IEEE Trans. Computers, 2004
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor.
Proceedings of the Field Programmable Logic and Application, 2004
2003
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the Progress in Artificial Intelligence, 2003
2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002
2001
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001
2000
J. Autom. Reason., 2000
Proceedings of the 2000 Design, 2000
1999
On Defect-Level Estimation and the Clustering Effect.
Proceedings of the VLSI: Systems on a Chip, 1999
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware.
Proceedings of the 36th Conference on Design Automation, 1999
1997
Proceedings of the European Design and Test Conference, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
1991
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991