Jose Renau

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

LiveHD: A Productive Live Hardware Development Flow.

[BibT_eX]

[DOI]

Sheng-Hong Wang

IEEE Micro, 2020

Load Driven Branch Predictor (LDBP).

[BibT_eX]

[DOI]

Akash Sridhar

Nursultan Kabylkas

CoRR, 2020

LiveSim: A Fast Hot Reload Simulator for HDLs.

[BibT_eX]

[DOI]

Sheng-Hong Wang

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

EMI Architectural Model and Core Hopping.

[BibT_eX]

[DOI]

Daphne I. Gorman

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SMatch: Structural Matching for Fast Resynthesis in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

GPU NTC Process Variation Compensation With Voltage Stacking.

[BibT_eX]

[DOI]

Alamelu Sankaranarayanan

José Luis Briz

IEEE Trans. Very Large Scale Integr. Syst., 2018

Automated Pipeline Transformations with Fluid Pipelines.

[BibT_eX]

[DOI]

Proceedings of the Advanced Logic Synthesis, 2018

2017

Architectural opportunities for novel dynamic EMI shifting (DEMIS).

[BibT_eX]

[DOI]

Daphne I. Gorman

Matthew R. Guthaus

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Liam: an actor based programming model for HDLs.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Level shifter design for voltage stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Timing speculative SRAM.

[BibT_eX]

[DOI]

Matthew R. Guthaus

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Managing Mismatches in Voltage Stacking with CoreUnfolding.

[BibT_eX]

[DOI]

José Luis Briz

ACM Trans. Archit. Code Optim., 2016

Analysis of PARSEC workload scalability.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

SRAM voltage stacking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Overhead of deoptimization checks in the V8 javascript engine.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Fluid Pipelines: Elastic circuitry meets Out-of-Order execution.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

LiveSim: Going live with microarchitecture simulation.

[BibT_eX]

[DOI]

Sina Hassani

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

LiveSynth: Towards an interactive synthesis flow.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015

Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication.

[BibT_eX]

[DOI]

Madan Mohan Das

ACM Trans. Archit. Code Optim., 2015

Message from the program chair.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2014

Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An energy efficient GPGPU memory hierarchy with tiny incoherent caches.

[BibT_eX]

[DOI]

Alamelu Sankaranarayanan

José Luis Briz

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

ESESC: A fast multicore simulator using Time-Based Sampling.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

ESESC: A fast performance, power, and temperature multicore simulator.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2012

Thermal-aware sampling in architectural simulation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011

ReRack: power simulation for data centers with renewable energy generation.

[BibT_eX]

[DOI]

Michael Brown

SIGMETRICS Perform. Evaluation Rev., 2011

Hot Chips 22.

[BibT_eX]

[DOI]

Will Eatherton

IEEE Micro, 2011

A design time simulator for computer architects.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Releasing efficient beta cores to market early.

[BibT_eX]

[DOI]

Rigo Dicochea

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

Characterizing processor thermal behavior.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009

SOI, interconnect, package, and mainboard thermal characterization.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Measuring and modeling variabilityusing low-cost FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008

Understanding bug fix patterns in verilog.

[BibT_eX]

[DOI]

Janaki T. Madhavan

E. James Whitehead Jr.

Proceedings of the 2008 International Working Conference on Mining Software Repositories, 2008

Processor Verification with hwBugHunt.

[BibT_eX]

[DOI]

Liying Su

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Measuring power and temperature from real processors.

[BibT_eX]

[DOI]

Michael Brown

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

System and Procesor Design Effort Estimation.

[BibT_eX]

[DOI]

Cyrus Bazeghi

Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Estimating design time for system circuits.

[BibT_eX]

[DOI]

Cyrus Bazeghi

Brian Greskamp

Josep Torrellas

Proceedings of the IFIP VLSI-SoC 2007, 2007

Effective Optimistic-Checker Tandem Core Design through Architectural Pruning.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Power model validation through thermal measurements.

[BibT_eX]

[DOI]

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Measuring performance, power, and temperature from real processors.

[BibT_eX]

[DOI]

Michael Brown

Proceedings of the Workshop on Experimental Computer Science, 2007

2006

CAVA: Using checkpoint-assisted value prediction to hide L2 misses.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2006

Energy-Efficient Thread-Level Speculation.

[BibT_eX]

[DOI]

IEEE Micro, 2006

POSH: a TLS compiler that exploits program structure.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2006

SEED: scalable, efficient enforcement of dependences.

[BibT_eX]

[DOI]

Michael C. Huang

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

uComplexity: Estimating Processor Design Effort.

[BibT_eX]

[DOI]

Cyrus Bazeghi

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Thread-Level Speculation on a CMP can be energy efficient.

[BibT_eX]

[DOI]

Proceedings of the 19th Annual International Conference on Supercomputing, 2005

2004

Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency

[BibT_eX]

[DOI]

PhD thesis, 2004

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2004

2003

Programming the FlexRAM parallel intelligent memory system.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2003

Positional Adaptation of Processors: Application to Energy Reduction.

[BibT_eX]

[DOI]

Michael C. Huang

Josep Torrellas

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002

Cherry: checkpointed early resource recycling in out-of-order microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Energy-efficient hybrid wakeup logic.

[BibT_eX]

[DOI]

Michael C. Huang