Jose Raul Garcia Ordaz

According to our database, Jose Raul Garcia Ordaz authored at least 7 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Dynamic CPU ISA customizations through FPGA interlays.

Jose Raul Garcia Ordaz

PhD thesis, 2018

A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine.

Jose Raul Garcia Ordaz, Dirk Koch

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017

HLS Compilation for CPU Interlays.

Jose Raul Garcia Ordaz, Dirk Koch

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

A security library for FPGA interlays.

Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit.

Jose Raul Garcia Ordaz, Dirk Koch

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric.

Jose Raul Garcia Ordaz, Dirk Koch

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2012

A Reorder Buffer Design for High Performance Processors.

Jose Raul Garcia Ordaz, Marco Antonio Ramírez Salinas, Luis A. Villa Vargas, Herón Molina Lozano, Cuauhtémoc Peredo Macías

Computación y Sistemas, 2012