José Pineda de Gyvez

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2021

A Low Power Fully-Digital Multi-Level Voltage Monitor Operating in a Wide Voltage Range for Energy Harvesting IoT.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

Heuristic Methods for Fine-Grain Exploitation of FDSOI.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Multi-Angle Fusion for Low-Cost Near-Field Ultrasonic in-Air Gesture Recognition.

[BibT_eX]

[DOI]

IEEE Access, 2020

Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power.

[BibT_eX]

[DOI]

Proceedings of the SLIP '20: System-Level Interconnect, 2020

An Electromagnetic Energy Harvester and Power Management in 28-nm FDSOI for IoT.

[BibT_eX]

[DOI]

Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

Mehran Mozaffari Kermani

IEEE Trans. Very Large Scale Integr. Syst., 2019

Enhancing sensitivity-based power reduction for an industry IC design context.

[BibT_eX]

[DOI]

Integr., 2019

Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs.

[BibT_eX]

[DOI]

Integr., 2019

Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

PRESS/HOLD/RELEASE Ultrasonic Gestures and Low Complexity Recognition Based on TCN.

[BibT_eX]

[DOI]

Emad A. Ibrahim

Min Li

Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Chip Health Tracking Using Dynamic In-Situ Delay Monitoring.

[BibT_eX]

[DOI]

Hadi Ahmadi Balef

Kees Goossens

Omar Alejandro Rodriguez Rosas

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Low power latch based design with smart retiming.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design.

[BibT_eX]

[DOI]

Kamlesh Singh

Hailong Jiao

Jos Huisken

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Logic Design Partitioning for Stacked Power Domains.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling.

[BibT_eX]

[DOI]

Kristof Blutman

Arjun Majumdar

Jacinto Garcia Martinez

Juan Diego Echeverri

Leo Sevat

Arnoud P. van der Wel

Kofi A. A. Makinwa

IEEE J. Solid State Circuits, 2017

Reconfigurable Support Vector Machine Classifier with Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

An analytical model for interdependent setup/hold-time characterization of flip-flops.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A scan-chain based state retention methodology for IoT processors operating on intermittent energy.

[BibT_eX]

[DOI]

Pascal Alexander Hager

Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Floorplan and placement methodology for improved energy reduction in stacked power-domain design.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A microcontroller with 96% power-conversion efficiency using stacked voltage domains.

[BibT_eX]

[DOI]

Kristof Blutman

Arjun Majumdar

Jacinto Garcia Martinez

Juan Diego Echeverri

Leo Sevat

Arnoud P. van der Wel

Kofi A. A. Makinwa

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Circuit valorization in the IC design ecosystem.

[BibT_eX]

[DOI]

Maarten Vertregt

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Lower power by voltage stacking: a fine-grained system design approach.

[BibT_eX]

[DOI]

Kristof Blutman

Jacinto Garcia Martinez

Balakrishnan Narayanaswamy

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

An Improved Methodology for Resilient Design Implementation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Supervised learning based model for predicting variability-induced timing errors.

[BibT_eX]

[DOI]

Xun Jiao

Abbas Rahimi

Rajesh K. Gupta

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Digital Systems Power Management for High Performance Mixed Signal Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Sub-threshold custom standard cell library validation.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Standard cell library tuning for variability tolerant designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Architectural Analysis for Wirelessly Powered Computing Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers.

[BibT_eX]

[DOI]

Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

2012

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS.

[BibT_eX]

[DOI]

Manuel J. Barragan Asian

IEEE Trans. Instrum. Meas., 2012

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters.

[BibT_eX]

[DOI]

Manuel J. Barragan Asian

J. Low Power Electron., 2012

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.

[BibT_eX]

[DOI]

Sebastian M. Londono

Proceedings of the IEEE 25th International SOC Conference, 2012

Sliding-Mode Control to Compensate PVT Variations in dual core systems.

[BibT_eX]

[DOI]

Alessandro Di Bucchianico

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Standard cell sizing for subthreshold operation.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs.

[BibT_eX]

[DOI]

Nick van der Meijs

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage.

[BibT_eX]

[DOI]

Bo Liu

Sebastian M. Londono

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Body bias driven design synthesis for optimum performance per area.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A forward body bias generator for digital CMOS circuits with supply voltage scaling.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

An energy-aware multiplier based on a Configurable-Reuse of points design methodology.

[BibT_eX]

[DOI]

Sebastian M. Londono

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

Calibration and Debugging of Multi-step Analog to Digital Converters.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm.

[BibT_eX]

[DOI]

Shaji Krishnan

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Statistical noise margin estimation for sub-threshold combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Efficient testing and diagnosis of faulty power switches in SOCs.

[BibT_eX]

[DOI]

Sandeep Kumar Goel

IET Comput. Digit. Tech., 2007

Vt balancing and device sizing towards high yield of sub-threshold static logic gates.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits.

[BibT_eX]

[DOI]

Manuel J. Barragan Asian

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique.

[BibT_eX]

[DOI]

Andrei Pavlov

Manoj Sachdev

IEEE J. Solid State Circuits, 2006

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.

[BibT_eX]

[DOI]

Josep Rius

J. Low Power Electron., 2006

Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

Testing and Diagnosis of Power Switches in SOCs.

[BibT_eX]

[DOI]

Sandeep Kumar Goel

Proceedings of the 11th European Test Symposium, 2006

2005

A capacitor cross-coupled common-gate low-noise amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Multi-VDD Testing for Analog Circuits.

[BibT_eX]

[DOI]

Rashid Amine

J. Electron. Test., 2005

Power-scan chain: design for analog testability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Functional vs. multi-VDD testing of RF circuits.

[BibT_eX]

[DOI]

Estella Silva

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Word line pulsing technique for stability fault detection in SRAM cells.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

On-chip digital power supply control for system-on-chip applications.

[BibT_eX]

[DOI]

Ralph Otten

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Glitch-free discretely programmable clock generation on chip.

[BibT_eX]

[DOI]

Francesco Pessolano

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Limits to performance spread tuning using adaptive voltage and body biasing.

[BibT_eX]

[DOI]

Francesco Pessolano

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Evaluation of signature-based testing of RF/analog circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Programmable techniques for cell stability test and debug in embedded SRAMs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Built-in current sensor for ΔIDDQ testing.

[BibT_eX]

[DOI]

Josep Rius Vázquez

IEEE J. Solid State Circuits, 2004

Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits.

[BibT_eX]

[DOI]

Hans Tuinhout

IEEE J. Solid State Circuits, 2004

Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs.

[BibT_eX]

[DOI]

Josep Rius Vázquez

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Low Energy Switch Block For FPGAs.

[BibT_eX]

[DOI]

Rohini Krishnan

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold.

[BibT_eX]

[DOI]

Andrei Pavlov

Manoj Sachdev

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Power Supply Ramping for Quasi-static Testing of PLLs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Technology exploration for adaptive power and frequency scaling in 90nm CMOS.

[BibT_eX]

[DOI]

Francesco Pessolano

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Low energy FPGA interconnect design.

[BibT_eX]

[DOI]

Rohini Krishnan

Martijn T. Bennebroek

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Power Supply Noise Monitor for Signal Integrity Faults.

[BibT_eX]

[DOI]

Josep Rius Vázquez

Proceedings of the 2004 Design, 2004

2003

Prelayout interconnect yield prediction.

[BibT_eX]

[DOI]

Phillip Christie

IEEE Trans. Very Large Scale Integr. Syst., 2003

Threshold Voltage Mismatch (DeltaVT) Fault Modeling.

[BibT_eX]

[DOI]

Antonio F. Mondragón-Torres

Rosa Rodríguez-Montañés

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

An Analog Integrated Circuit Design Laboratory.

[BibT_eX]

[DOI]

Terry Mayhugh Jr.

José Silva-Martínez

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

VDD Ramp Testing for RF Circuits.

[BibT_eX]

[DOI]

Rashid Amine

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Encoded-Low Swing Technique for Ultra Low Power Interconnect.

[BibT_eX]

[DOI]

Rohini Krishnan

Harry J. M. Veendrick

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Process-variability aware delay fault testing of ΔVT and weak-open defects.

[BibT_eX]

[DOI]

Daniel Arumí-Delgado

Rosa Rodríguez-Montañés

Proceedings of the 8th European Test Workshop, 2003

2002

Resistance Characterization for Weak Open Defects.

[BibT_eX]

[DOI]

Rosa Rodríguez-Montañés

Paul Volf

IEEE Des. Test Comput., 2002

2001

Average Leakage Current Estimation of CMOS Logic Circuits.

[BibT_eX]

[DOI]

Eric van de Wetering

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Yield modeling and BEOL fundamentals.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Pre-layout prediction of interconnect manufacturability.

[BibT_eX]

[DOI]

Phillip Christie

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

2000

Full-signature real-time corrosion detection of underground casing pipes.

[BibT_eX]

[DOI]

Jiming Yin

Mi Lu

IEEE Trans. Instrum. Meas., 2000

Nonlinear Computability Based on Chaos.

[BibT_eX]

[DOI]

Gabriele Manganaro

Int. J. Bifurc. Chaos, 2000

Real-time wavelet-integrated corrosion detection system for casing pipes.

[BibT_eX]

[DOI]

Jiming Yin

Mi Lu

Integr. Comput. Aided Eng., 2000

Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families.

[BibT_eX]

[DOI]

Madhuban Kishor

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999

Subband coding and image compression using CNN.

[BibT_eX]

[DOI]

Oscar Moreira-Tamayo

Int. J. Circuit Theory Appl., 1999

CMOS cryptosystem using a Lorenz chaotic oscillator.

[BibT_eX]

[DOI]

Octavio A. González

Gunhee Han

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Chaotic generation of PN sequences: a VLSI implementation.

[BibT_eX]

[DOI]

A. Dornbusch

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

Time multiplexed color image processing based on a CNN with cell-state outputs.

[BibT_eX]

[DOI]

Lei Wang

IEEE Trans. Very Large Scale Integr. Syst., 1998

1996

Color image processing in a cellular neural-network environment.

[BibT_eX]

[DOI]

Chi-Chien Lee

IEEE Trans. Neural Networks, 1996

Time-Multiplexing Scheme for Cellular Neural Networks Based Image Processing.

[BibT_eX]

[DOI]

Apollo Q. Fong

Ajay Kanji

Real Time Imaging, 1996

Preprocessing operators for image compression using cellular neural networks.

[BibT_eX]

[DOI]

Oscar Moreira-Tamayo

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995

Time Domain Analog Wavelet Transform in Real-Time.

[BibT_eX]

Oscar Moreira-Tamayo

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Universal Interface Between PC and Neural Networks Hardware.

[BibT_eX]

[DOI]

Apollo Q. Fong

Ajay Kanji

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

A power supply ramping and current measurement based technique for analog fault diagnosis.

[BibT_eX]

[DOI]

Shyam S. Somayajula

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Behavioral Testing of Cellular Neural Networks.

[BibT_eX]

[DOI]

John Willis

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Time-Mulitplexing CNN Simulator.

[BibT_eX]

[DOI]

Chi-Chien Lee

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Single-Layer CNN Simulator.

[BibT_eX]

[DOI]

Chi-Chien Lee

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Integrated circuit defect-sensitivity - theory and computational models.

[BibT_eX]

The Kluwer international series in engineering and computer science 208, Kluwer, ISBN: 978-0-7923-9306-1, 1993

1992

IC defect sensitivity for footprint-type spot defects.

[BibT_eX]

[DOI]

Chennian Di

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1989

On the design and implementation of a wafer yield editor.

[BibT_eX]

[DOI]

Jochen A. G. Jess

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

A layout defect-sensitivity extractor.

[BibT_eX]

[DOI]