Jose Moreira
Orcid: 0000-0001-7029-6327
According to our database1,
Jose Moreira
authored at least 11 papers
between 2007 and 2023.
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Bibliography
2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2020
Bandwidth Optimized Parallel Algorithms for Sparse Matrix-Matrix Multiplication using Propagation Blocking.
Proceedings of the SPAA '20: 32nd ACM Symposium on Parallelism in Algorithms and Architectures, 2020
Proceedings of the Dynamic Data Driven Applications Systems, 2020
2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
An Active Test Fixture Approach for 40 Gbps and Above At-Speed Testing Using a Standard ATE System.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
Proceedings of the 2012 IEEE International Test Conference, 2012
An Active Test Fixture Approach for Testing 28 Gbps Applications Using a Lower Data Rate ATE System.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Design of a High Bandwidth Interposer for Performance Evaluation of ATE Test Fixtures at the DUT Socket.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Development of an ATE test cell for at-speed characterization and production testing.
Proceedings of the 2011 IEEE International Test Conference, 2011
2008
Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment.
Proceedings of the 2008 IEEE International Test Conference, 2008
2007
Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications.
Proceedings of the 2007 IEEE International Test Conference, 2007