José Miguel Mora-Gutiérrez

Orcid: 0000-0003-2790-0087

According to our database1, José Miguel Mora-Gutiérrez authored at least 9 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
TinyJAMBU Hardware Implementation for Low Power.
IEEE Access, 2024

VLSI integration of a RO-based PUF into a 65 nm technology.
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2021
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.
Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.
IEEE Access, 2021

2020
ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium.
IEEE Trans. Circuits Syst., 2020

2017
Multiradix Trivium Implementations for Low-Power IoT Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Trivium hardware implementations for power reduction.
Int. J. Circuit Theory Appl., 2017

2013
An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Low Power Implementation of Trivium Stream Cipher.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012


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