José Miguel Mora-Gutierrez

According to our database, José Miguel Mora-Gutierrez authored at least 8 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

TinyJAMBU Hardware Implementation for Low Power.

Carlos Fernández-García, José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández

IEEE Access, 2024

2021

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández

Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.

Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández

IEEE Access, 2021

2020

ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

IEEE Trans. Circuits Syst., 2020

2017

Multiradix Trivium Implementations for Low-Power IoT Hardware.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

IEEE Trans. Very Large Scale Integr. Syst., 2017

Trivium hardware implementations for power reduction.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

Int. J. Circuit Theory Appl., 2017

2013

An adaptive approach to on-chip CMOS ramp generation for high resolution single-slope ADCs.

Samuel Sordo Ibáñez, Blanca Piñero-García, Servando Espejo-Meana, Antonio Ragel-Morales, Joaquin Ceballos Caceres, Manuel Munoz-Diaz, Luis Carranza-González, Alberto Arias-Drake, José Miguel Mora-Gutierrez, Miguel Ángel Lagos-Florido

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

Low Power Implementation of Trivium Stream Cipher.

José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012