Jose Maiz

According to our database, Jose Maiz authored at least 2 papers between 2003 and 2004.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2004

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V_T CMOS process.

Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar

IEEE J. Solid State Circuits, 2004

2003

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process.

Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003