José M. Ferreira
Orcid: 0000-0002-6181-4118Affiliations:
- University of Porto, FEUP, Portugal
According to our database1,
José M. Ferreira
authored at least 34 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE Global Engineering Education Conference, 2024
2023
Proceedings of the IEEE Global Engineering Education Conference, 2023
2022
An Innovative Course Delivery Model for Industry-Master Programs - Presentation of a Case-Study at the University of South-Eastern Norway.
Proceedings of the IEEE Global Engineering Education Conference, 2022
2020
Use of XR technologies to bridge the gap between Higher Education and Continuing Education.
Proceedings of the 2020 IEEE Global Engineering Education Conference, 2020
2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
2011
Microelectron. J., 2011
Microprocess. Microsystems, 2011
2008
Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution.
IEEE Trans. Very Large Scale Integr. Syst., 2008
A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of 11th IEEE International Conference on Emerging Technologies and Factory Automation, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Proceedings of 10th IEEE International Conference on Emerging Technologies and Factory Automation, 2005
2003
Proceedings of the 2003 Design, 2003
2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs.
Proceedings of the 2002 Design, 2002
Proceedings of the Groupware: Design, Implementation and Use, 8th International Workshop, 2002
2001
Dynamically Rotate And Free for Test: The Path for FPGA Concurrent Test.
Proceedings of the 2nd Latin American Test Workshop, 2001
DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
2000
Implementing a Self-Checking PROFIBUS Slave.
Proceedings of the 1st Latin American Test Workshop, 2000
1999
From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Board-level prototype validation: a built-in controller and extended BST architecture.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 4th European Test Workshop, 1999
1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the European Design Automation Conference 1993, 1993