José Luis Imaña
Orcid: 0000-0002-4220-4111
According to our database1,
José Luis Imaña
authored at least 33 papers
between 2003 and 2024.
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Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024
Future Internet, August, 2024
Falcon/Kyber and Dilithium/Kyber Network Stack on Nvidia's Data Processing Unit Platform.
IEEE Access, 2024
First Line-rate End-to-End Post-Quantum Encrypted Optical Fiber Link Using Data Processing Units (DPUs).
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024
Proceedings of the 24th International Conference on Transparent Optical Networks, 2024
2023
Domain-oriented masked bit-parallel finite-field multiplier against side-channel attacks.
Inf. Process. Lett., August, 2023
Hardware architecture of Dillon's APN permutation for different primitive polynomials.
Microprocess. Microsystems, 2023
2022
Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Emerg. Top. Comput., 2022
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the Arithmetic of Finite Fields - 9th International Workshop, 2022
Work-in-Progress: High-Performance Systolic Hardware Accelerator for RBLWE-based Post-Quantum Cryptography.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Computers, 2021
Quantum Inf. Process., 2021
2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2018
IEEE Trans. Computers, 2018
Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2016
High-Speed Polynomial Basis Multipliers Over GF(2<sup>m</sup>) for Special Pentanomials.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
2013
Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations.
IEEE Trans. Ind. Electron., 2013
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials.
Integr., 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2011
Modular Multiplication and Exponentiation Architectures for Fast RSA Cryptosystem Based on Digit Serial Computation.
IEEE Trans. Ind. Electron., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
2010
Intell. Inf. Manag., 2010
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
2006
Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields <i>GF</i>(2<sup><i>m</i></sup>) Generated by AOPs.
J. VLSI Signal Process., 2006
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Computers, 2006
2004
Reconfigurable implementation of bit-parallel multipliers over GF(2<sup>m</sup>) for two classes of finite fields.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004
2003
A New Reconfigurable-Oriented Method for Canonical Basis Multiplication over a Class of Finite Fields GF(2<sup>m</sup>).
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003