Jose Luis Garcia-Gervacio

According to our database, Jose Luis Garcia-Gervacio authored at least 13 papers between 2008 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations.

Gilberto Domínguez Rodríguez, Jose Luis Garcia-Gervacio, Héctor Vázquez-Leal

IEICE Electron. Express, 2018

TCAD analysis and modeling for NBTI mechanism in FinFET transistors.

Alfonso Herrera-Moreno, Jose Luis Garcia-Gervacio, Héctor Villacorta-Minaya, Héctor Vázquez-Leal

IEICE Electron. Express, 2018

2016

SCADA system design: A proposal for optimizing a production line.

Jose Adrian Ruiz Carmona, Julio Cesar Munoz Benitez, Jose Luis Garcia-Gervacio

Proceedings of the 2016 International Conference on Electronics, 2016

2015

Screening small-delay defects using inter-path correlation to reduce reliability risk.

Jose Luis Garcia-Gervacio, Alejandro Nocua, Víctor H. Champac

Microelectron. Reliab., 2015

Low V_DD and body bias conditions for testing bridge defects in the presence of process variations.

Hector Villacorta, Jose Luis Garcia-Gervacio, Jaume Segura, Víctor H. Champac

Microelectron. J., 2015

2014

Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies.

Jose Luis Garcia-Gervacio, Jaime Martínez-Castillo, Víctor H. Champac

Proceedings of the 15th Latin American Test Workshop, 2014

2013

Voltage Regulation System for UHF RFID Tags.

Jose Luis Garcia-Gervacio, Agustín Leobardo Herrera-May, Gregorio Zamora-Mejía, Jaime Martínez-Castillo, Alejandro Díaz-Sánchez

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias.

Hector Villacorta, Jose Luis Garcia-Gervacio, Víctor H. Champac, Sebastià A. Bota, Jaime Martínez-Castillo, Jaume Segura

Proceedings of the 14th Latin American Test Workshop, 2013

2012

Small-delay defects detection under process variation using Inter-Path Correlation.

Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011

Computing the Detection Probability for Small Delay Defects of Nanometer ICs.

Jose Luis Garcia-Gervacio, Víctor H. Champac

J. Electron. Test., 2011

2010

Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs.

Jose Luis Garcia-Gervacio, Víctor H. Champac

Proceedings of the 15th European Test Symposium, 2010

2009

Detectability analysis of small delays due to resistive opens considering process variations.

Jose Luis Garcia-Gervacio, Víctor H. Champac

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008

A design methodology for logic paths tolerant to local intra-die variations.

Daniel Iparraguirre-Cardenas, Jose Luis Garcia-Gervacio, Víctor H. Champac

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008