José Luís Almada Güntzel

According to our database1, José Luís Almada Güntzel authored at least 20 papers between 1999 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Squarer exploration for energy-efficient sum of squared differences.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy-efficient SATD for beyond HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Rate-constrained successive elimination of Hadamard-based SATDs.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
An analytical timing-driven algorithm for detailed placement.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2013
Real-time digital modulation classification based on Support Vector Machines.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Quality assessment of subsampling patterns for pel decimation targeting high definition video.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo, 2013

2012
Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Cache-tuning-aware scratchpad allocation from binaries.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

2010
A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2009
Mapping Data and Code into Scratchpads from Relocatable Binaries.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2006
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2004
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.
Proceedings of the Integrated Circuit and System Design, 2004

Physical design methodologies for performance predictability and manufacturability.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
A New Macro-cell Generation Strategy for three metal layer CMOS Technologies.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Improving Critical Path Identification in Functional Timing Analysis.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits.
Proceedings of the Integrated Circuit and System Design, 2003

1999
Designing a Mask Programmable Matrix for Sequential Circuits.
Proceedings of the VLSI: Systems on a Chip, 1999


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