Jose Isaza-Gonzalez

According to our database, Jose Isaza-Gonzalez authored at least 6 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Evaluation of fault injection tools for reliability estimation of microprocessor-based embedded systems.

Alexander Aponte-Moreno, José Isaza-González, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle

Microprocess. Microsystems, February, 2023

2020

An Experimental Comparison of Fault Injection Tools for Microprocessor-based Systems.

Alexander Aponte-Moreno, José Isaza-González, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle

Proceedings of the IEEE Latin-American Test Symposium, 2020

2018

SHARC: An efficient metric for selective protection of software against soft errors.

Jose Isaza-Gonzalez, Felipe Restrepo-Calle, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi

Microelectron. Reliab., 2018

2017

Contrast of a HDL model and COTS version of a microprocessor for soft-error testing.

Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A. Aguirre

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2016

Dependability evaluation of COTS microprocessors via on-chip debugging facilities.

Jose Isaza-Gonzalez, Alejandro Serrano-Cases, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez

Proceedings of the 17th Latin-American Test Symposium, 2016

On the influence of compiler optimizations in the fault tolerance of embedded systems.

Alejandro Serrano-Cases, Jose Isaza-Gonzalez, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016