Jose Fernando Zazo

According to our database, Jose Fernando Zazo authored at least 8 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Understanding PCIe performance for end host networking.

Rolf Neugebauer, Gianni Antichi, José Fernando Zazo, Yury Audzevich, Sergio López-Buedo, Andrew W. Moore

Proceedings of the 2018 Conference of the ACM Special Interest Group on Data Communication, 2018

dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter.

Maciej Bielski, Ilias Syrigos, Kostas Katrinis, Dimitris Syrivelis, Andrea Reale, Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisis N. Pnevmatikatos, E. H. Pap, George Zervas, Vaibhawa Mishra, Arsalan Saljoghei, Alvise Rigo, Jose Fernando Zazo, Sergio López-Buedo, Martí Torrents, Ferad Zyulkyarov, Michael Enrico, Óscar González de Dios

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links.

Jose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks.

Mario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis.

Carlos Vega, Jose Fernando Zazo, Hugo Meyer, Ferad Zyulkyarov, Sergio López-Buedo, Javier Aracil

Proceedings of the 19th IEEE International Conference on High Performance Computing and Communications; 15th IEEE International Conference on Smart City; 3rd IEEE International Conference on Data Science and Systems, 2017

2016

Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications.

Jose Fernando Zazo, Sergio López-Buedo, Gustavo Sutter, Javier Aracil

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

2015

A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances.

Jose Fernando Zazo, Sergio López-Buedo, Yury Audzevich, Andrew W. Moore

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014

TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces.

Jose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014