José E. Schutt-Ainé

According to our database, José E. Schutt-Ainé authored at least 18 papers between 1988 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A new pre-conditioned STDP rule and its hardware implementation in neuromorphic crossbar array.

Tuomin Tao, Da Li, Hanzhi Ma, Yan Li, Shurun Tan, En-Xiao Liu, José E. Schutt-Ainé, Er-Ping Li

Neurocomputing, November, 2023

Modeling and Analysis of Spike Signal Sequence for Memristor Crossbar Array in Neuromorphic Chips.

Tuomin Tao, Hanzhi Ma, Da Li, Yan Li, Shurun Tan, En-Xiao Liu, José E. Schutt-Ainé, Er-Ping Li

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

2021

Thin-Film Transistor Simulations With the Voltage-In-Current Latency Insertion Method.

Wei Chun Chin, Andrei Pashkovich, José E. Schutt-Ainé, Nur Syazreen Ahmad, Patrick Goh

IEEE Access, 2021

2020

PAM-4 Behavioral Modeling using Machine Learning via Laguerre-Volterra Expansion.

Xinying Wang, Thong Nguyen, José E. Schutt-Ainé

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019

Fast Transient Simulation of High-Speed Channels Using Recurrent Neural Network.

Thong Nguyen, Tianjian Lu, Ken Wu, José E. Schutt-Ainé

CoRR, 2019

An Improved Algorithm for Drift Diffusion Transport and Its Application on Large Scale Parallel Simulation of Resistive Random Access Memory Arrays.

Da-Wei Wang, Wenchao Chen, Wen-Sheng Zhao, Guo-Dong Zhu, Zhen-Guo Zhao, José E. Schutt-Ainé, Wen-Yan Yin

IEEE Access, 2019

Fully Coupled Electrothermal Simulation of Large RRAM Arrays in the "Thermal-House".

Da-Wei Wang, Wenchao Chen, Wen-Sheng Zhao, Guo-Dong Zhu, Kai Kang, Pingqi Gao, José E. Schutt-Ainé, Wen-Yan Yin

IEEE Access, 2019

LIM Algorithms for MOSFET Models.

José E. Schutt-Ainé, Patrick Goh

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018

A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.

Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu

IEEE J. Solid State Circuits, 2018

2013

Phase-locked loop simulations using the latency insertion method.

José E. Schutt-Ainé, Patrick Goh

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2007

Topological realizability conditions and their interpretation for admittance matrices of an MTL system with mode delays.

Josh G. Nickel, José E. Schutt-Ainé

J. Frankl. Inst., 2007

2001

High-frequency characterization of twisted-pair cables.

José E. Schutt-Ainé

IEEE Trans. Commun., 2001

Scanning the issue interconnections - addressing the next challenge of IC technology (part II: design, characterization, and modeling).

José E. Schutt-Ainé, Sung-Mo Kang

Proc. IEEE, 2001

Interconnections-addressing the next challenge of IC technology (part I: integration and packaging trends).

José E. Schutt-Ainé, Sung-Mo Kang

Proc. IEEE, 2001

1997

Transient analysis of diode switching circuits using asymptotic waveform evaluation.

Wendemagegnehu T. Beyene, José E. Schutt-Ainé

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1993

Modeling Interconnections with Nonlinear Discontinuities.

José E. Schutt-Ainé, Kyung-soo Oh

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Difference Model Approach for the Transient Simulation of Transmission Lines.

Dimitri Kuznetsov, José E. Schutt-Ainé

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1988

Modeling and Simulation of High-Speed Digital Circuit Interconnections

José E. Schutt-Ainé

PhD thesis, 1988