Jose Cisneros
Orcid: 0000-0002-5497-7103
According to our database1,
Jose Cisneros
authored at least 7 papers
between 2017 and 2024.
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Bibliography
2024
A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full-Band Raw-Signal Recording.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 16-Ch CMI-Tolerant Neural AFE with Inherent CM Detection and Shared CM Suppression Achieving 0.006mm2/Ch and 3.1μW/Ch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2021
A 1024-Channel 10-Bit 36-$\mu$W/ch CMOS ROIC for Multiplexed GFET-Only Sensor Arrays in Brain Mapping.
IEEE Trans. Biomed. Circuits Syst., 2021
2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Switch-Less Frequency-Domain Multiplexing of GFET Sensors and Low-Power CMOS Frontend for 1024-Channel μECoG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A Compact Switched-Capacitor Multi-Bit Quantizer for Low-Power High-Resolution Delta-Sigma ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation.
Sensors, 2017