Jose Cayo

According to our database, Jose Cayo authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

An Advanced Memory WRITE Algorithm to Mitigate the Effects of ReRAM Cell Variability.

Vicente Ramirez, Jose Cayo, Ioannis Vourkas

Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

2023

On the Development of Prognostics and System Health Management (PHM) Techniques for ReRAM Applications.

Jose Cayo, Matias Melivilu, Antonio Rubio, Ioannis Vourkas

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

2022

A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM.

Jose Cayo, Ioannis Vourkas, Antonio Rubio

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2021

Design Steps towards a MCU-based Instrumentation System for Memristor-based Crossbar Arrays.

Jose Cayo, Ioannis Vourkas

Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021