José-Ángel Gregorio

Concurr. Comput. Pract. Exp., 2020

SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads.

[BibT_eX]

[DOI]

Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

2019

CLASSIC: A cortex-inspired hardware accelerator.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation.

[BibT_eX]

[DOI]

CoRR, 2019

Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

2018

Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

Mosaic: A Scalable Coherence Protocol.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2018

2017

An adaptive cache coherence protocol: Trading storage for traffic.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2017

2016

AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

CLAASIC: a Cortex-Inspired Hardware Accelerator.

[BibT_eX]

[DOI]

CoRR, 2016

2015

Improving last level shared cache performance through mobile insertion policies (MIP).

[BibT_eX]

[DOI]

Parallel Comput., 2015

Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2013

LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

CMP off-chip bandwidth scheduling guided by instruction criticality.

[BibT_eX]

[DOI]

Pablo Prieto

Proceedings of the International Conference on Supercomputing, 2013

Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

The case for a scalable coherence protocol for complex on-chip cache hierarchies in many-core systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012

Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Balancing Performance and Cost in CMP Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

The Necessity for Hardware QoS Support for Server Consolidation and Cloud Computing

[BibT_eX]

[DOI]

Javier Merino

CoRR, 2012

LOCKE Detailed Specification Tables

[BibT_eX]

[DOI]

CoRR, 2012

TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Improving coherence protocol reactiveness by trading bandwidth for latency.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011

Multilevel Cache Modeling for Chip-Multiprocessor Systems.

[BibT_eX]

[DOI]

Pablo Prieto

IEEE Comput. Archit. Lett., 2011

2010

ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture.

[BibT_eX]

[DOI]

Javier Merino

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009

MRR: Enabling fully adaptive multicast routing for CMP interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008

Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

SP-NUCA: a cost effective dynamic non-uniform cache architecture.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2008

Improving the performance of large interconnection networks using congestion-control mechanisms.

[BibT_eX]

[DOI]

José Miguel-Alonso

Cruz Izu

Perform. Evaluation, 2008

Reducing the Interconnection Network Cost of Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

2007

Immucube: Scalable Fault-Tolerant Routing for k-ary n-cube Networks.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2007

Rotary router: an efficient architecture for CMP interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006

High-performance adaptive routing for networks with arbitrary topology.

[BibT_eX]

[DOI]

J. Syst. Archit., 2006

Effects of Injection Pressure on Network Throughput.

[BibT_eX]

[DOI]

Cruz Izu

José Miguel-Alonso

Proceedings of the 14th Euromicro International Conference on Parallel, 2006

Topic 13: Routing and Communication in Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

2005

Evaluation of Interconnection Network Performance Under Heavy Non-uniform Loads.

[BibT_eX]

[DOI]

Cruz Izu

José Miguel-Alonso

Proceedings of the Distributed and Parallel Computing, 2005

2004

Evaluating kilo-instruction multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Parallelization of a Neural Net Training Program in a Grid Environment.

[BibT_eX]

[DOI]

Alejandro Gutiérrez

Rafael Menéndez de Llano

Francisco Cavero

Proceedings of the 12th Euromicro Workshop on Parallel, 2004

Simulation Methodology for Decision Support Workloads.

[BibT_eX]

[DOI]

Luis A. Amigo

Proceedings of the 12th Euromicro Workshop on Parallel, 2004

Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Load Unbalance in k-ary n-Cube Networks.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2004 Parallel Processing, 2004

A first glance at Kilo-instruction based multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the First Conference on Computing Frontiers, 2004

2003

On the Design of a High-Performance Adaptive Router for CC-NUMA Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2003

Chordal Topologies for Interconnection Networks.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 5th International Symposium, 2003

A Low Cost Fault Tolerant Packet Routing for Parallel Computers.

[BibT_eX]

[DOI]

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002

Modeling of interconnection subsystems for massively parallel computers.

[BibT_eX]

[DOI]

Fernando Vallejo

Perform. Evaluation, 2002

SICOSYS: An Integrated Framework for studying Interconnection Network Performance in Multiprocessor Systems.

[BibT_eX]

[DOI]

Proceedings of the 10th Euromicro Workshop on Parallel, 2002

2001

The Adaptive Bubble Router.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2001

A new routing mechanism for networks with irregular topology.

[BibT_eX]

[DOI]

Proceedings of the 2001 ACM/IEEE conference on Supercomputing, 2001

A New Communication Mechanism for Cluster Computing.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000

A case study of trace-driven simulation for analyzing interconnection networks: cc-NUMAs with ILP processors.

[BibT_eX]

[DOI]

Proceedings of the Eight Euromicro Workshop on Parallel and Distributed Processing, 2000

Pipelining Router Design Improves Parallel System Performance.

[BibT_eX]

[DOI]

Carmen Carrión

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

Improving parallel system performance by changing the arrangement of the network links.

[BibT_eX]

[DOI]

Proceedings of the 14th international conference on Supercomputing, 2000

1999

Performance evaluation of the bubble algorithm: benefits for k-ary n-cubes.

[BibT_eX]

[DOI]

Carmen Carrión

Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

Low-level router design and its impact on supercomputer system performance.

[BibT_eX]

[DOI]

Proceedings of the 13th international conference on Supercomputing, 1999

Adaptive Bubble Router: A Design to Improve Performance in Torus Networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Processing 1999, 1999

Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998

Ghost packets: a deadlock-free solution for k-ary n-cube networks.

[BibT_eX]

[DOI]

Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

1997

A flow control mechanism to avoid message deadlock in k-ary n-cube networks.

[BibT_eX]

[DOI]

Proceedings of the Fourth International on High-Performance Computing, 1997

1996

A two-level programming strategy for distributed systems.

[BibT_eX]

[DOI]

D. Conde

Rafael Menéndez de Llano

Michael González Harbour

Microprocess. Microprogramming, 1996

Assessing the Performance of the New IBM SP2 Communication Subsystem.

[BibT_eX]

[DOI]

IEEE Parallel Distributed Technol. Syst. Appl., 1996

1995

Petri Net Modeling of Interconnection Networks for Massively Parallel Architectures.

[BibT_eX]

[DOI]

Proceedings of the 9th international conference on Supercomputing, 1995

1994

Shared Memory Multimicroprocessor Operating System with an Extended Petri Net Model.

[BibT_eX]

[DOI]

Fernando Vallejo

Michael González Harbour

José M. Drake

IEEE Trans. Parallel Distributed Syst., 1994

1992

Performance Evaluation of Parallel Systems by Using Unbounded Generalized Stochastic Petri Nets.

[BibT_eX]

[DOI]

Mercedes Granda

José M. Drake