José Ángel Díaz-Madrid
According to our database1,
José Ángel Díaz-Madrid
authored at least 14 papers
between 2003 and 2024.
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Bibliography
2024
A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors.
J. Real Time Image Process., July, 2024
2023
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2021
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC.
Circuits Syst. Signal Process., 2021
2020
J. Real Time Image Process., 2020
Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2018
Int. J. Circuit Theory Appl., 2018
2017
An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2013
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels.
Int. J. Circuit Theory Appl., 2013
2010
Int. J. Circuit Theory Appl., 2010
2009
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits.
Proceedings of the Nature Inspired Problem-Solving Methods in Knowledge Engineering, 2007
2003
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003
An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks.
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003