José Alejandro Galaviz-Aguilar
Orcid: 0000-0002-6550-124X
According to our database1,
José Alejandro Galaviz-Aguilar
authored at least 12 papers
between 2014 and 2024.
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Bibliography
2024
Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers.
IEEE Embed. Syst. Lett., September, 2024
2022
A Comparison of Surrogate Behavioral Models for Power Amplifier Linearization under High Sparse Data.
Sensors, 2022
A Crest Factor Reduction Technique for LTE Signals with Target Relaxation in Power Amplifier Linearization.
Sensors, 2022
Reliable comparison for power amplifiers nonlinear behavioral modeling based on regression trees and random forest.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Automated Driving of GaN Chireix Power Amplifier for the Digital Predistortion Linearization.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
Int. J. Circuit Theory Appl., 2020
IET Commun., 2020
IEEE Access, 2020
IEEE Access, 2020
2019
Comparison of a genetic programming approach with ANFIS for power amplifier behavioral modeling and FPGA implementation.
Soft Comput., 2019
2015
Modeling memory effects in RF power amplifiers applied to a digital pre-distortion algorithm and emulated on a DSP-FPGA board.
Integr., 2015
2014
Measure-based modeling and FPGA implementation of RF Power Amplifier using a multi-layer perceptron neural network.
Proceedings of the 24th International Conference on Electronics, 2014