Jos van Sas

According to our database1, Jos van Sas authored at least 12 papers between 1989 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

1996
Towards an Effective I<sub>DDQ</sub> Test Vector Selection and Application Methodology.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Coping with Re-usability Using Sequential ATPG: A Practical Case Study.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Cellular automata based deterministic self-test strategies for programmable data paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Design of a C-testable booth multiplier using a realistic fault model.
J. Electron. Test., 1994

An Off-chip I<sub>DDQ</sub> Current Measurement Unit for Telecommunication ASICs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories.
IEEE Des. Test Comput., 1993

BIST for Embedded Static RAMs with Coverage Calculation.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992
Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment.
Proceedings of the conference on European design automation, 1991

1990
Testability strategy and test pattern generation for register files and customized memories.
Microprocess. Microsystems, 1990

Cellular automata based self-test for programmable data paths.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
A testability strategy for multiprocessor architecture.
IEEE Des. Test, 1989


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