Joris Lacord
According to our database1,
Joris Lacord
authored at least 8 papers
between 2012 and 2022.
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Bibliography
2022
Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the IEEE International Memory Workshop, 2022
2021
Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
2020
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications.
CoRR, 2020
2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2014
The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012