Jorgen Peddersen
Orcid: 0000-0001-5952-769X
According to our database1,
Jorgen Peddersen
authored at least 28 papers
between 2005 and 2020.
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Bibliography
2020
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2015
RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Proceedings of the 25th International Conference on VLSI Design, 2012
2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2010
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM.
Des. Autom. Embed. Syst., 2010
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2010
Proceedings of The Ninth IEEE International Symposium on Networking Computing and Applications, 2010
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.
Proceedings of the Design, Automation and Test in Europe, 2010
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.
Proceedings of the 47th Design Automation Conference, 2010
2009
Proceedings of the 34th Annual IEEE Conference on Local Computer Networks, 2009
LOP: a novel SRAM-based architecture for low power and high throughput packet classification.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
PhD thesis, 2008
IEEE Des. Test Comput., 2008
2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005